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authorAaditya Dhruv <[email protected]>2023-01-02 17:39:03 +0530
committerAaditya Dhruv <[email protected]>2023-01-02 17:39:03 +0530
commit4383c0ef6e6c7e0637d5027741777812bc25da95 (patch)
tree8700a85b9ad63f31eeeb2fe0836bac37344c7a4b
parent871034cd7eeca56c82bd3b142b264d0655afa864 (diff)
todo complete: dxyn out of bounds handle
-rw-r--r--src/lib.rs3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/lib.rs b/src/lib.rs
index b97bcd2..32c1cde 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -271,15 +271,16 @@ impl Chip {
fn drw_dxyn(&mut self) {
let x = self.registers[self.x] as u32 % WIDTH; //x-coord
let y = self.registers[self.y] as u32 % HEIGHT; //y-coord
- //TODO: Cover up for end of bounds
//for every row
for i in 0..self.n {
//for every bit (column)
for j in 0..8 {
//get idx in display
+ if (y + i as u32) < HEIGHT && (x + j) < WIDTH {
let idx = (((y + i as u32) * WIDTH) + x+j) as usize;
//XOR the bit
self.display[idx] ^= self.mem[(self.index + i as u16) as usize] as u16 >> (7 - j) & 1; //7 - j for reverse bit shifting
+ }
}
}
}