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authorAaditya Dhruv <[email protected]>2023-01-02 12:27:06 +0530
committerAaditya Dhruv <[email protected]>2023-01-02 12:27:06 +0530
commite2315ff7b9a94e8f823e347a4c76d5b74a9cdc0b (patch)
tree1eb3a8ee9f0c3c3a50dd16efa85e6569bc85d64d
parente77a756082ea8ef1e37b00fc1f4ea8eb0ac7fa2f (diff)
removed test file, fixed rendering bug - XOR was in reverse
-rw-r--r--pinkan1
-rw-r--r--src/lib.rs12
2 files changed, 7 insertions, 6 deletions
diff --git a/pinkan b/pinkan
deleted file mode 100644
index 119927e..0000000
--- a/pinkan
+++ /dev/null
@@ -1 +0,0 @@
-Pooki
diff --git a/src/lib.rs b/src/lib.rs
index 60c9295..381281c 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -153,14 +153,16 @@ impl Chip {
let x = self.registers[self.x as usize] as u32 % WIDTH;
let y = self.registers[self.y as usize] as u32 % HEIGHT;
- println!("{}, {}, {}", x, y, self.n);
for i in 0..self.n {
- println!("#{:b}", self.mem[(self.index + i as u16) as usize] as u16);
- println!("{}", i);
+ let start_index = (((y + i as u32) * WIDTH) + x) as usize;
+ let slice = &self.display[start_index..start_index+8];
for j in 0..8 {
- self.display[(((y + i as u32) * WIDTH) + x+j) as usize] ^= self.mem[(self.index + i as u16) as usize] as u16 >> j & 1;
-// println!("{}", self.mem[(self.index + i as u16) as usize] as u16 >> j & 1);
+ let idx = (((y + i as u32) * WIDTH) + x+j) as usize;
+ let prev = self.display[idx];
+ self.display[idx] ^= self.mem[(self.index + i as u16) as usize] as u16 >> (7 - j) & 1;
}
+ let start_index = (((y + i as u32) * WIDTH) + x) as usize;
+ let slice = &self.display[start_index..start_index+8];
}
}