diff options
author | Aaditya Dhruv <[email protected]> | 2023-12-29 15:41:31 -0600 |
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committer | Aaditya Dhruv <[email protected]> | 2023-12-29 15:41:31 -0600 |
commit | 45fec56a9ee8231fb129f4250f24e8bceefd6eec (patch) | |
tree | ca9c635a00f6fddcaf54ef8f0c18dc7c4bf0658f | |
parent | 4ffc735eeb6c5148b7255a954ea36f91cdb777cf (diff) |
Add partial opcode implementation
-rw-r--r-- | src/cpu/chip.rs | 87 |
1 files changed, 83 insertions, 4 deletions
diff --git a/src/cpu/chip.rs b/src/cpu/chip.rs index 4866ff7..ed373b3 100644 --- a/src/cpu/chip.rs +++ b/src/cpu/chip.rs @@ -75,11 +75,27 @@ impl Chip { for i in 0..self.rom_bank_0.len() { self.rom_bank_0[i] = rom_buf.get(i).unwrap().to_owned(); } + self.pc = 0x0100; + } + pub fn write_memory(&mut self, pc: usize, value: u8) { + match pc { + 0x0000..=0x3fff => { println!("ROM Bank 0"); self.rom_bank_0[pc as usize] = value }, //Fixed bank, rom_bank_0 + 0x4000..=0x7fff => { println!("ROM Bank 1"); self.rom_bank_n[pc as usize - 0x4000] = value }, + 0x8000..=0x9fff => { }, + 0xa000..=0xbfff => { }, + 0xc000..=0xcfff => { }, + 0xd000..=0xdfff => { }, + 0xfe00..=0xfe9f => { }, + 0xff00..=0xff7f => { }, + 0xff80..=0xfffe => { }, + 0xffff..=0xffff => { }, + _ => { } + }; } pub fn read_memory(&self, pc: usize) -> u8 { let address = match pc { - 0x0000..=0x3fff => { self.rom_bank_0[self.pc as usize] }, //Fixed bank, rom_bank_0 - 0x4000..=0x7fff => { self.rom_bank_n[self.pc as usize - 0x4000] }, + 0x0000..=0x3fff => { println!("ROM Bank 0"); self.rom_bank_0[pc as usize] }, //Fixed bank, rom_bank_0 + 0x4000..=0x7fff => { println!("ROM Bank 1"); self.rom_bank_n[pc as usize - 0x4000] }, 0x8000..=0x9fff => { 0x0 }, 0xa000..=0xbfff => { 0x0 }, 0xc000..=0xcfff => { 0x0 }, @@ -98,12 +114,75 @@ impl Chip { let arg2 = self.read_memory(self.pc as usize + 2); self.byte2 = arg1; self.byte3 = arg2; + println!("Instr: 0x{:02X}", self.instr); self.pc += 1; + println!("0x{:02X?}", &self.rom_bank_0[self.pc as usize..(self.pc + 10) as usize]); + } + + pub fn execute(&mut self) { + let mut next = 0; + + match self.instr { + 0x00 => { println!("NOOP!") } + 0x32 => { self.ldd_hl_a() } + 0x0e | 0x06 => { self.ld_rr(); next = 1; } + 0xc3 => { self.jmp_nn() } + 0xa8..=0xaf => { self.xor_r() } + 0x01 | 0x11 | 0x21 | 0x31 => { self.ld_rr_nn(); next = 2; }, + _ => { println!("Error: 0x{:02X} not implemented!", self.instr); std::process::exit(1); } + } + self.pc += next; + } + + fn ld_rr(&mut self) { + match self.instr { + 0x0e => { self.c = self.byte2 }, + 0x06 => { self.b = self.byte2 }, + _ => {}, + } + } + + fn ldd_hl_a(&mut self) { + let mut pc = ((self.h as u16) << 8) as u16 | self.l as u16; + self.write_memory(pc as usize, self.a); + pc -= 1; + self.h = (pc >> 8) as u8; + self.l = (pc << 8 >> 8) as u8; + } + + fn xor_r(&mut self) { + let value = match self.instr & 0x0f { + 0x8 => { self.b }, + 0x9 => { self.c }, + 0xa => { self.d }, + 0xb => { self.e }, + 0xc => { self.h }, + 0xd => { self.l }, + 0xe => { + let ptr = ((self.h as u16) << 8) as u16 | self.l as u16; + self.read_memory(ptr as usize) + }, + 0xf => { self.a }, + _ => { panic!("Wrong register read for XOR_R") } + }; + self.a = self.a ^ value; + self.flags.zero = (self.a == 0) as u8 + } + + fn jmp_nn(&mut self) { + println!("{:02X}, {:02X}", self.byte2, self.byte3); + self.pc = ((self.byte3 as u16) << 8) as u16 | self.byte2 as u16; + println!("Jumping to 0x{:02X}", self.pc); } - pub fn execute(&self) { + fn ld_rr_nn(&mut self) { match self.instr { - _ => { panic!("Error: 0x{:02X} not implemented!", self.instr) } + 0x01 => { self.b = self.byte3; self.c = self.byte2; }, //BC = nn (nn = MSB << 8 | LSB) + 0x11 => { self.d = self.byte3; self.e = self.byte2; }, //DE = nn (nn = MSB << 8 | LSB) + 0x21 => { self.h = self.byte3; self.l = self.byte2; }, //HL = nn (nn = MSB << 8 | LSB) + 0x31 => { self.sp = ((self.byte3 as u16) << 8) as u16 | self.byte2 as u16 }, //HL = nn (nn = MSB << 8 | LSB) + _ => { }, } } + } |