path: root/src/cpu/chip.rs

use std::fs::File;
use std::io::Read;


#[derive(Debug)]
pub struct Flags {
    pub zero: u8, //Zero flag
    pub n: u8, //Subtraction flag (BCD)
    pub h: u8, //Half carry flag (BCD)
    pub carry: u8, //Carry flag
}

impl Flags {
    fn new() -> Self {
        Flags {
            zero: 0,
            n: 0,
            h: 0,
            carry: 0,
        }
    }
}

#[derive(Debug)]
pub struct Chip {
    pub a: u8, //Upper bits of AF, the Accumulator
    pub b: u8,
    pub c: u8,
    pub d: u8,
    pub e: u8,
    pub h: u8,
    pub l: u8,
    pub instr: u8, //Current instruction
    pub sp: u16, //Stack pointer
    pub pc: u16, //Program counter
    pub byte2: u8,
    pub byte3: u8,
    pub flags: Flags, //Lower bits of AF, Flags register
    pub rom_bank_0: [u8; 16384],
    pub rom_bank_n: [u8; 16384],
    pub external_ram_bank_n: [u8; 8192],
    pub wram_bank_0: [u8; 4096],
    pub wram_bank_n: [u8; 4096],
    pub rom: Vec<u8>,

}

impl Chip {
    pub fn new() -> Self {
        Chip {
            a: 0,
            b: 0,
            c: 0,
            d: 0,
            e: 0,
            h: 0,
            l: 0,
            instr: 0,
            sp: 0,
            pc: 0,
            byte2: 0,
            byte3: 0,
            flags: Flags::new(),
            rom_bank_0: [0; 16384],
            rom_bank_n: [0; 16384],
            external_ram_bank_n: [00; 8192],
            wram_bank_0: [0; 4096],
            wram_bank_n: [0; 4096],
            rom: Vec::new(),
        }
    }
    pub fn load_rom(&mut self, rom_path: &str) {
        let mut rom = File::open(rom_path).unwrap_or_else(|_err| panic!("Valid ROM needed!"));
        rom.read_to_end(&mut self.rom).unwrap_or_else(|_err| panic!("Error reading ROM"));

	for i in 0..self.rom_bank_0.len() {
            self.rom_bank_0[i] = self.rom.get(i).unwrap().to_owned();
        }
        self.pc = 0x0100;
    }
    pub fn write_memory(&mut self, pc: u16, value: u8) {
        match pc {
            0x0000..=0x3fff => { println!("Writing: ROM Bank 0"); self.rom_bank_0[pc as usize] = value  }, //Fixed bank, rom_bank_0
            0x4000..=0x7fff => { println!("Writing: ROM Bank 1"); self.rom_bank_n[pc as usize - 0x4000] = value },
            0x8000..=0x9fff => {  },
            0xa000..=0xbfff => {  },
            0xc000..=0xcfff => {  },
            0xd000..=0xdfff => {  },
            0xfe00..=0xfe9f => {  },
            0xff00..=0xff7f => {  },
            0xff80..=0xfffe => {  },
            0xffff..=0xffff => {  },
            _ => {  }
        };
    }
    pub fn read_memory(&self, pc: usize) -> u8 {
        let address = match pc {
            0x0000..=0x3fff => { println!("ROM Bank 0"); self.rom_bank_0[pc as usize]  }, //Fixed bank, rom_bank_0
            0x4000..=0x7fff => { println!("ROM Bank 1"); self.rom_bank_n[pc as usize - 0x4000] },
            0x8000..=0x9fff => { 0x0 },
            0xa000..=0xbfff => { 0x0 },
            0xc000..=0xcfff => { 0x0 },
            0xd000..=0xdfff => { 0x0 },
            0xfe00..=0xfe9f => { 0x0 },
            0xff00..=0xff7f => { 0x0 },
            0xff80..=0xfffe => { 0x0 },
            0xffff..=0xffff => { 0x0 },
            _ => { 0xff }
        };
        address
    }
    pub fn fetch(&mut self) {
        self.instr = self.read_memory(self.pc as usize);
        let arg1 = self.read_memory(self.pc as usize + 1);
        let arg2 = self.read_memory(self.pc as usize + 2);
        self.byte2 = arg1;
        self.byte3 = arg2;
        println!("Instr: 0x{:02X}", self.instr);
        self.pc += 1;
        println!("0x{:02X?}", &self.rom_bank_0[self.pc as usize..(self.pc + 10) as usize]);
    }

    //Lookup the u8 register table to get the u16 address we want to look at. We are constructing the address
    //to read/write from/to based on this table
    fn get_r16_register_address(&self, register_code: u8) -> u16 {
        //Example
        // reg b = 0x00ca
        // reg c = 0x00fe
        // reg b << 8 = 0xca00
        // bitwise OR with reg c results in 0xcafe
        match register_code {
            0b001 => { (self.b as u16) << 8 | self.c as u16 },
            0b011 => {  (self.d as u16) << 8 | self.e as u16 },
            0b101 => {(self.h as u16) << 8 | self.l as u16 },
            0b111 => { self.sp },
            _ => { panic!("Cannot get register address: Unknown register code {}", register_code) }
        }
    }

    // Write a 16 bit value to a pair of registers based on the usual pairing
    fn set_r16_register_address(&mut self, register_code: u8, value: u16) {
        let high = (value >> 8) as u8;
        let low = (value & 0xff) as u8;
        match register_code {
            0b001 => { self.b = high; self.c = low; },
            0b011 => {  self.d = high; self.e = low; },
            0b101 => { self.h = high; self.l = low; },
            0b111 => { self.sp = value; },
            _ => { panic!("Cannot set register address: Unknown register code {}", register_code) }
        };
    }
    // Get the memory address pointed to by a register pair. This is basically the r16mem table
    // This returns a 16 bit memory address
    fn get_r16_register_memory_address(&mut self, register_code: u8) -> u16 {

        match register_code {
            0b001 => { (self.b as u16) << 8 | self.c as u16 },
            0b011 => {  (self.d as u16) << 8 | self.e as u16 },
            0b101 => {
                let hl = (self.h as u16) << 8 | self.l as u16; //Get current HL value
                self.set_r16_register_address(0b101, hl+1); //Increment HL value and set it back to HL (ptr++)
                hl //Return HL
            },
            0b111 => {
                let hl = (self.h as u16) << 8 | self.l as u16; //Get current HL value
                self.set_r16_register_address(0b101,